998f3a27be
In the short term there might be devices with Sandy Bridge CPUs on mainboards with Panther Point PCHes. While this configuration option is perfectly valid, coreboot currently ties Sandy Bridge to Cougar Point and Ivy Bridge to Panther Point. One occurence is in the ME handling code. To make coreboot most flexible, compile both ME handlers into coreboot and decide at runtime which one to use. Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1280 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
43 lines
1.3 KiB
Makefile
43 lines
1.3 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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driver-y += pch.c
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driver-y += azalia.c
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driver-y += lpc.c
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driver-y += pci.c
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driver-y += pcie.c
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driver-y += sata.c
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driver-y += usb_ehci.c
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driver-y += me.c
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driver-y += me_8.x.c
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driver-y += smbus.c
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ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-y += spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-y += reset.c
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