8e515d36b4
This makes it available early in romstage without having to worry when the different romstagse enable it. Check for extended CMOS to be enabled in early romstage. This is used by a later commit which uses the extended CMOS region for stoage. Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1306 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
78 lines
2 KiB
C
78 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/tsc.h>
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#include "pch.h"
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static void store_initial_timestamp(void)
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{
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/* On Cougar Point we have two 32bit scratchpad registers available:
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* D0:F0 0xdc (SKPAD)
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* D31:F2 0xd0 (SATA SP)
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*/
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tsc_t tsc = rdtsc();
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pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
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pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
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}
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(void)
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{
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u8 reg8;
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device_t dev;
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dev = PCI_DEV(0, 0x1f, 0);
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reg8 = pci_read_config8(dev, 0xdc);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(dev, 0xdc, reg8);
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}
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static void enable_port80_on_lpc(void)
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{
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device_t dev = PCI_DEV(0, 0x1f, 0);
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/* Enable port 80 POST on LPC */
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pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
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#if 0
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RCBA32(GCS) &= (~0x04);
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#else
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volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
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u32 reg32 = *gcs;
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reg32 = reg32 & ~0x04;
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*gcs = reg32;
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#endif
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}
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static void bootblock_southbridge_init(void)
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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store_initial_timestamp();
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#endif
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enable_spi_prefetch();
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enable_port80_on_lpc();
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/* Enable upper 128bytes of CMOS */
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RCBA32(RC) = (1 << 2);
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}
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