coreboot-kgpe-d16/src/soc
Patrick Rudolph 9a016236d4 soc/intel/skylake/vr_config: Add loadline defaults
In addition to zero IccMax specified by mainboard with socketed CPU, allow
a zero LoadLine default.
The SoC code will fill in the default AC/DC LoadLine values are per
datasheets:

* "7th Generation Intel® Processor Families for H Platforms, Vol 1"
  Document Number: 335190-003
* "7th Generation Intel® Processor Families for S Platforms and
  Intel ®Core™ X-Series Processor Family, Vol 1"
  Document Number: 335195-003

The AC/DC LoadLine is CPU and board specific.
TODO: Find out how to get the LoadLine from vendor firmware and find out
how to map those to different CPU LoadLines.

Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 11:14:47 +00:00
..
amd amd/picasso: Unify SMM relocation 2019-08-16 00:37:31 +00:00
cavium src: Include <stdint.h> instead of <inttypes.h> 2019-08-10 01:33:58 +00:00
imgtec arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
intel soc/intel/skylake/vr_config: Add loadline defaults 2019-08-20 11:14:47 +00:00
mediatek arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
nvidia arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
qualcomm arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
rockchip src: Include <stdint.h> instead of <inttypes.h> 2019-08-10 01:33:58 +00:00
samsung arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
sifive soc/sifive/fu540: add code for spi and map flash to memory spaces 2019-08-12 08:35:17 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00