9bc041187d
With CSE-lite enabled, we were going through the lengthy memory training procedure twice on the first power-on boot or after full BIOS SPI flash update. This moves the global reset performed to achieve the CSE-lite RO to RW reboot to a later boot phase so that it happens after the memory training data has been written to the MRC cache. Now, the 2nd (and subsequent) reboot can utilize the memory training data established during the 1st boot. This reduces the first boot time by about 20s on a 16GB system. Looking at the timing stats form cbmem, the normal boot penalty is about 300ms - mostly attributed to running FspSiliconInit a 2nd time. We will get this time back when the mrc_cache refactoring effort lands (cb:44196, et. al). BUG=b:162021048 TEST=Booted on volteer, confirmed 20s faster boot time. Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> |
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| apollolake | ||
| baytrail | ||
| braswell | ||
| broadwell | ||
| cannonlake | ||
| common | ||
| denverton_ns | ||
| icelake | ||
| jasperlake | ||
| quark | ||
| skylake | ||
| tigerlake | ||
| xeon_sp | ||
| Kconfig | ||