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coreboot-kgpe-d16/src/soc/intel
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Werner Zeh 9d18e330fd siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC 
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 22:41:45 +02:00
..
apollolake soc/intel/apollolake: Add functions to calculate GPIO address 2016-09-09 23:51:01 +02:00
baytrail src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
braswell Makefile.inc: Use $(MAINBOARDDIR) 2016-09-04 05:33:25 +02:00
broadwell src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
common lpss_i2c: Increase default timeout to 4ms 2016-09-04 05:31:37 +02:00
fsp_baytrail fsp_baytrail: Refactor code for SPI debug messages 2016-09-06 21:17:59 +02:00
fsp_broadwell_de siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC 2016-09-12 22:41:45 +02:00
quark src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
sch src/soc: Remove unnecessary whitespace before "\n" and "\t" 2016-08-28 18:25:14 +02:00
skylake Makefile.inc: Use $(MAINBOARDDIR) 2016-09-04 05:33:25 +02:00