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coreboot-kgpe-d16/src/soc/rockchip/rk3399
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Lin Huang 9dc00ef625 rockchip/rk3399: set CA drive strength to 48ohms 
As shown in testing, if CA use 34.3ohms drive strength, it leads
to an overshoot. To fix this, change the drive strength to 48 ohms.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358761
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15811
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:57:55 +02:00
..
include/soc rockchip/rk3399: extend romstage range 2016-07-15 00:38:15 +02:00
bl31_plat_params.c rockchip: rk3399: pass board specific message to BL31 2016-06-12 12:14:36 +02:00
bootblock.c rockchip/rk3399: initialize apll_b 2016-07-12 00:27:52 +02:00
chip.h rockchip: rk3399: initialize display for eDP 2016-06-03 18:08:10 +02:00
clock.c rockchip/rk3399: initialize apll_b 2016-07-12 00:27:52 +02:00
display.c rockchip: rk3399: initialize display for eDP 2016-06-03 18:08:10 +02:00
emmc.c rockchip: rk3399: enable sdhci clk for emmc 2016-05-18 20:23:42 +02:00
gpio.c rockchip/rk3399: Fix pinctrl pull bias settings 2016-07-12 00:28:33 +02:00
Kconfig Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices 2016-06-12 12:11:08 +02:00
Makefile.inc gru: implement hw reset function 2016-07-18 20:14:07 +02:00
mmu_operations.c rockchip: rk3399: enable mmu 2016-05-09 08:42:04 +02:00
romstage.c rockchip/rk3399: set kevin rev3 pwm regulator initial value to 0.95v 2016-07-15 00:38:04 +02:00
saradc.c rockchip: rk3399: support saradc 2016-05-09 08:46:42 +02:00
sdram.c rockchip/rk3399: set CA drive strength to 48ohms 2016-07-25 18:57:55 +02:00
soc.c soc: Remove newline from CHIP_NAME 2016-07-07 17:14:01 +02:00
timer.c
tsadc.c rockchip: rk3399: add tsadc driver 2016-05-18 20:19:29 +02:00
usb.c rockchip: gru: Add USB DRD DWC3 controller support 2016-06-12 12:10:22 +02:00