Arthur Heymans a1cc557d61 soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ... Add a soc specific callback for getting the IIO IOAPIC enumeration ID. Tested on ocp/deltalake. Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>		2020-11-16 11:07:16 +00:00
..
alderlake	soc/intel/alderlake: Add PCH ID 0x5181	2020-11-12 03:51:49 +00:00
apollolake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
broadwell	soc/intel/broadwell/systemagent.c: Rename to northbridge.c	2020-11-16 11:06:30 +00:00
cannonlake	soc/intel/cnl: enable ACPI CPPC entries generation	2020-11-14 18:54:35 +00:00
common	soc/intel/common/block: add code for ACPI CPPC entries generation	2020-11-14 18:54:23 +00:00
denverton_ns	soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device	2020-11-02 06:28:50 +00:00
elkhartlake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
icelake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
jasperlake	soc/intel/jasperlake: Log PM event from an internal device	2020-11-10 06:20:04 +00:00
quark	arch/x86: Introduce ARCH_ALL_STAGES_X86_32	2020-09-26 11:42:28 +00:00
skylake	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	2020-11-13 17:32:37 +00:00
tigerlake	lp4x: Add new memory parts and generate SPDs	2020-11-16 11:01:02 +00:00
xeon_sp	soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's	2020-11-16 11:07:16 +00:00
Kconfig