a444753596
Fix the following errors and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent ERROR: do not use assignment in if condition WARNING: Statements terminations use 1 semicolon WARNING: unnecessary whitespace before a quoted newline WARNING: else is not generally useful after a break or return TEST=Build for reef Change-Id: I5486936dbf19b066c76179d929660affa1da5f16 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <soc/cpu.h>
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#include <console/console.h>
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#include <delay.h>
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#include "chip.h"
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unsigned long tsc_freq_mhz(void)
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{
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msr_t msr = rdmsr(MSR_PLATFORM_INFO);
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return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
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}
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void set_max_freq(void)
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{
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msr_t msr, msr_rd;
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unsigned int eax;
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eax = cpuid_eax(CPUID_LEAF_PM);
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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eax &= 0x2;
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if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
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/* Burst Mode has been factory configured as disabled
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* and is not available in this physical processor
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* package.
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*/
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printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
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return;
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}
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/* Enable burst mode */
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msr.hi &= ~APL_BURST_MODE_DISABLE;
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Enable speed step. */
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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msr.lo |= 1 << 16;
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Set P-State ratio */
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msr = rdmsr(IA32_PERF_CTL);
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msr.lo &= ~0xff00;
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/* Read the frequency limit ratio and set it properly in PERF_CTL */
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msr_rd = rdmsr(FREQ_LIMIT_RATIO);
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msr.lo |= (msr_rd.lo & 0xff) << 8;
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wrmsr(IA32_PERF_CTL, msr);
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}
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