Update default ODT config to have correct CA ODT settings as the
current defaults are incorrect for all the current apollolake designs.
All the current designs pull both A and B channels' LPDDR4 modules' ODT
pins to 1.1V. Therefore, the correct impedance setting needs to be
applied.
In order for the settings to take effect one needs to clear the
memory training cache in deployed systems. Trigger this by bumping
the memory setting version for the SoC.
If needed in the future support for allowing the override of this
setting from the mainboard should be straight forward. It's just not
necessary at this time.
BUG=b:37687843
TEST=BAT test, warm, reboot, S3 cycle test
Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19397
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
a3d13fbd69