coreboot-kgpe-d16/src/soc/intel/skylake
Aaron Durbin a3d36bd969 skylake: read out and report full width of gen_pmcon registers
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and
save the full 32 bits for completeness.

BUG=chrome-os-partner:42847
BRANCH=None
TEST=Built and booted. Noted output on terminal.

Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0
Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286270
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21 21:11:11 +02:00
..
acpi skylake: remove whitespace from ASL files 2015-07-17 21:37:32 +02:00
bootblock
include/soc skylake: read out and report full width of gen_pmcon registers 2015-07-21 21:11:11 +02:00
microcode soc/intel: Remove microcode terminators 2015-07-17 23:05:17 +02:00
romstage skylake: read out and report full width of gen_pmcon registers 2015-07-21 21:11:11 +02:00
acpi.c
chip.c
chip.h skylake: Show SPI controller if enabled in devicetree.cb 2015-07-21 20:05:26 +02:00
cpu.c
cpu_info.c
elog.c
finalize.c
flash_controller.c
gpio.c
igd.c
Kconfig Glados: Update Serial IO modes in devicetree 2015-07-21 20:23:25 +02:00
lpc.c
Makefile.inc
memmap.c intel fsp: remove CHIPSET_RESERVED_MEM_BYTES 2015-07-21 20:09:31 +02:00
monotonic_timer.c
pch.c
pcie.c
pcr.c
pei_data.c
pmc.c
pmutil.c
ramstage.c
smbus.c
smbus_common.c
smi.c
smihandler.c
smmrelocate.c
systemagent.c intel fsp: remove CHIPSET_RESERVED_MEM_BYTES 2015-07-21 20:09:31 +02:00
tsc_freq.c
uart.c Skylake: Only support UART2 as debug port, clean up the rest 2015-07-21 20:10:19 +02:00
xhci.c