Felix Held a5cdf75f69 soc/amd: move warm reset flag function prototypes to common code ... Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-03-11 15:11:20 +00:00
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acpi	soc/amd/cezanne/acpi: Add globalnvs.asl	2021-02-25 23:41:53 +00:00
include/soc	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
acpi.c	soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings	2021-02-26 23:45:22 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry	2021-02-13 17:09:11 +00:00
chip.c	soc/amd/cezanne/chip: add soc_acpi_name	2021-02-18 01:15:55 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chipset.cb	soc/amd/cezanne: Add USB ports to chipset.cb	2021-03-10 23:47:03 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
cpu.c	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
data_fabric.c	soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries	2021-02-16 00:08:06 +00:00
early_fch.c	soc/amd/cezanne: Disable legacy DMA IO ports	2021-03-02 22:17:20 +00:00
fch.c	soc/amd/cezanne: Add PCI IRQ Router definitions	2021-02-12 20:42:35 +00:00
fsp_params.c	soc,vendorcode/amd/cezanne: add basic FSP integration	2021-01-24 18:15:46 +00:00
fw.cfg	soc/amd/cezanne: Add PSP whitelist debug unlock support	2021-03-01 08:27:57 +00:00
gpio.c	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	2021-02-10 01:31:28 +00:00
Kconfig	soc/amd/cezanne: Add USB ports to chipset.cb	2021-03-10 23:47:03 +00:00
Makefile.inc	mb/amd/majolica: Update to use proper APCBs built for Majolica	2021-03-10 23:28:19 +00:00
pcie_gpp.c	soc/amd/cezanne/pcie_gpp: add pci_driver for external root ports	2021-02-17 18:52:16 +00:00
reset.c	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
romstage.c	soc/amd/cezanne: select common APOB NV cache code	2021-03-10 20:44:45 +00:00
root_complex.c	soc/amd/cezanne/acpi: Add pci0.asl	2021-02-22 07:29:31 +00:00
smihandler.c	soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support	2021-03-10 00:30:15 +00:00
smu.c	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
uart.c	soc/amd/cezanne/uart: write ACPI tables	2021-02-17 10:35:26 +00:00