Aaron Durbin a6e9051bc6 lib/coreboot_table: use the architecture dependent table size ... Utilize the architecture dependent coreboot table size value from <arch/cbconfig.h> Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14455 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)		2016-05-02 20:03:34 +02:00
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acpi	acpi/: add missing license header	2016-01-14 22:52:11 +01:00
arch	lib/coreboot_table: use the architecture dependent table size	2016-05-02 20:03:34 +02:00
commonlib	ensure correct byte ordering for cbfs segment list	2016-04-25 23:30:00 +02:00
console	arch/x86: introduce postcar stage/phase	2016-03-23 14:24:30 +01:00
cpu	soc/intel/apollolake: Add cache for BIOS ROM	2016-04-28 05:45:37 +02:00
device	payloads: add iPXE 'payload' build	2016-04-13 17:45:37 +02:00
drivers	drivers/intel/i210: Use uint8_t and friends instead of u8	2016-04-28 08:25:23 +02:00
ec	kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme	2016-04-19 18:34:18 +02:00
include	lib/reg_script: Allow multiple independent handlers	2016-04-30 20:44:58 +02:00
lib	lib/coreboot_table: use the architecture dependent table size	2016-05-02 20:03:34 +02:00
mainboard	mb/emulation/*/board_info.txt: Update QEMU URL	2016-05-01 16:25:01 +02:00
northbridge	nb/amd/mct_ddr3: Only initialize ECC bits once	2016-05-02 16:17:52 +02:00
soc	lib/reg_script: Allow multiple independent handlers	2016-04-30 20:44:58 +02:00
southbridge	intel/i82801ax: Fix IDE setup console log	2016-04-22 17:25:19 +02:00
superio	superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox	2016-04-13 23:39:28 +02:00
vendorcode	drivers/intel/i210: Use uint8_t and friends instead of u8	2016-04-28 08:25:23 +02:00
Kconfig	lib/coreboot_table: use the architecture dependent table size	2016-05-02 20:03:34 +02:00