Nico Huber a74af56dc1 Overhaul speedstep code ... This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2012-11-05 21:24:36 +01:00
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amd	AMD agesa: add enable cache at the end of disable_cache_as_ram	2012-11-02 21:04:28 +01:00
intel	Overhaul speedstep code	2012-11-05 21:24:36 +01:00
via	VIA Nano: Add support for VIA Nano CPUs	2012-09-05 03:43:02 +02:00
x86	Synchronize rdtsc instructions	2012-08-09 00:38:39 +02:00
Kconfig	buildsystem: Make CPU microcode updating more configurable	2012-09-05 03:40:47 +02:00
Makefile.inc	buildsystem: Make CPU microcode updating more configurable	2012-09-05 03:40:47 +02:00