bbbfbf2e0f
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
101 lines
3 KiB
C
101 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/io.h>
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#include <cbmem.h>
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#include <device/pci.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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size_t mmap_region_granluarity(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
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/* Align to TSEG size when SMM is in use */
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if (CONFIG_SMM_TSEG_SIZE != 0)
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return CONFIG_SMM_TSEG_SIZE;
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/* Make it 8MiB by default. */
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return 8 << 20;
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}
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static void *smm_region_start(void)
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{
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/*
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* SMM base address matches the top of DPR. The DPR register has
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* 1 MiB alignment and reports the TOP of the DPR range.
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*/
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uint32_t smm_base = pci_read_config32(SA_DEV_ROOT, DPR);
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smm_base = ALIGN_DOWN(smm_base, 1 << 20);
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return (void *)smm_base;
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}
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void smm_region(void **start, size_t *size)
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{
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*start = smm_region_start();
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*size = mmap_region_granluarity();
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}
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void *cbmem_top(void)
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{
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/*
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* +-------------------------+ Top of RAM (aligned)
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* | System Management Mode |
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* | code and data | Length: CONFIG_TSEG_SIZE
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* | (TSEG) |
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* +-------------------------+ SMM base (aligned)
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* | |
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* | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
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* | |
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* +-------------------------+ top_of_ram (aligned)
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* | |
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* | CBMEM Root |
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* | |
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* +-------------------------+
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* | |
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* | FSP Reserved Memory |
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* | |
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* +-------------------------+
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* | |
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* | Various CBMEM Entries |
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* | |
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* +-------------------------+ top_of_stack (8 byte aligned)
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* | |
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* | stack (CBMEM Entry) |
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* | |
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* +-------------------------+
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*/
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unsigned long top_of_ram = (unsigned long)smm_region_start();
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/*
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* Subtract DMA Protected Range size if enabled and align to a multiple
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* of TSEG size.
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*/
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u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
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if (dpr & DPR_EPM) {
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top_of_ram -= (dpr & DPR_SIZE_MASK) << 16;
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top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity());
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}
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return (void *)top_of_ram;
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}
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