Paul Menzel b06f8ddfe8 Documentation/riscv: Improve index.md

1.  Add dot/period to the end of sentences
2.  Remove blank line at the end of the file
3.  Break lines after 75 characters
4.  Use RISC-V spelling
5.  Add comma for clarity

Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28654
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2018-10-30 02:10:44 +00:00

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RISC-V architecture documentation

This section contains documentation about coreboot on RISC-V architecture.

Mode usage

All stages run in M mode.

Payloads have a choice of managing M mode activity: they can control everything or nothing.

Payloads run from the romstage (i.e. rampayloads) are started in M mode. The payload must, for example, prepare and install its own SBI.

Payloads run from the ramstage are started in S mode, and trap delegation will have been done. These payloads rely on the SBI and can not replace it.

Stage handoff protocol

On entry to a stage or payload,

all harts are running.
A0 is the hart ID.
A1 is the pointer to the Flattened Device Tree (FDT).

Additional payload handoff requirements

The location of cbmem should be placed in a node in the FDT.

Trap delegation

Traps are delegated in the ramstage.

SMP within a stage

At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore. At the end of the stage harts 1..max are released by changing the semaphore.

A possible way to do this is to have a pointer to a struct containing variables, e.g.

struct blocker {
	void (*fn)(); // never returns
}

The hart blocks until fn is non-null, and then calls it. If fn returns, we will panic if possible, but behavior is largely undefined.

Only hart 0 runs through most of the code in each stage.

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