coreboot-kgpe-d16/src
Joel Kitching 2c8243cf6d drivers/intel/fsp2_0: fix TPM setup and MRC cache hash logic
When VBOOT_STARTS_IN_BOOTBLOCK is selected, the tpm_setup call
in memory_init.c is not used.

When VBOOT_STARTS_IN_ROMSTAGE is selected, the tpm_setup call
in memory_init.c is triggered.  However, when verstage runs,
tpm_setup is called yet again, and an error is triggered from
the multiple initialization calls.

Since there are currently no boards using
VBOOT_STARTS_IN_ROMSTAGE + FSP2_0_USES_TPM_MRC_HASH, disable
this combination via Kconfig, and remove the tpm_setup call
from Intel FSP memory initializion code.

* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=y
  vboot is enabled, and TPM is setup prior to Intel FSP memory
  initialization.  Allow FSP2_0_USES_TPM_MRC_HASH option.

* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=n
  vboot is enabled, but TPM is setup in romstage, after Intel
  FSP memory initialization.  Disallow FSP2_0_USES_TPM_MRC_HASH
  option.

* VBOOT=n
  vboot is disabled.  Disallow FSP2_0_USES_TPM_MRC_HASH option.

See bug for more information:
https://bugs.chromium.org/p/chromium/issues/detail?id=940377

BUG=chromium:940377
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I4ba91c275c33245be61041cb592e52f861dbafe6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 20:23:03 +00:00
..
acpi
arch arch/x86: Fix PCI IO config accessor 2019-03-14 11:49:43 +00:00
commonlib vboot: copy data structures to CBMEM for downstream use 2019-03-14 11:47:28 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
device device/pci_ops: Rename 'where' to 'reg' 2019-03-13 04:42:05 +00:00
drivers drivers/intel/fsp2_0: fix TPM setup and MRC cache hash logic 2019-03-15 20:23:03 +00:00
ec ec/google/wilco: Clear S0ix support bit at boot 2019-03-15 15:31:59 +00:00
include vboot: copy data structures to CBMEM for downstream use 2019-03-14 11:47:28 +00:00
lib Remove leftover files 2019-03-14 11:32:06 +00:00
mainboard mb/google/hatch: Enable TBMC device 2019-03-15 13:12:22 +00:00
northbridge src: Drop unused 'include <arch/ioapic.h>' 2019-03-13 07:29:01 +00:00
security vboot: rename symbols for better consistency 2019-03-15 12:59:29 +00:00
soc soc/intel/cannonlake: Fix GEN_PMCON bit checks 2019-03-15 19:52:30 +00:00
southbridge sb/via/common: Fix indirect includes 2019-03-15 05:02:35 +00:00
superio Remove leftover files 2019-03-14 11:32:06 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake 2019-03-15 12:47:30 +00:00
Kconfig Kconfig: Add system type entries for common enclosures 2019-02-05 16:03:29 +00:00