Paul Fagerburg ae1e14e438 helios: Add TEMP_SENSOR4 to DPTF ... Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to the DPTF. BRANCH=None BUG=b:142266102 TEST=`emerge-hatch coreboot` Verify that Helios builds correctly. Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>		2019-10-15 16:15:25 +00:00
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acpi
arch	arch/x86: Don't allow separate verstage to boot from romcc bootblock	2019-10-08 11:41:06 +00:00
commonlib	device,drivers/: Drop some __SIMPLE_DEVICE__ use	2019-09-30 11:07:46 +00:00
console	src/: Replace some __PRE_RAM__ use	2019-09-14 11:16:17 +00:00
cpu	nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK	2019-10-13 12:46:18 +00:00
device	device: Use scan_static_bus() over scan_lpc_bus()	2019-10-08 12:59:56 +00:00
drivers	drivers/spi: ignore -Wvla on clang too	2019-10-09 22:15:18 +00:00
ec	ec/acpi/ec.c Link EC code in bootblock & verstage	2019-10-12 12:57:04 +00:00
include	SMBIOS (Type 17): Add HBM device type and DIE form factor value	2019-10-09 10:40:56 +00:00
lib	fmap: Add get_fmap_flash_offset()	2019-09-27 21:59:44 +00:00
mainboard	helios: Add TEMP_SENSOR4 to DPTF	2019-10-15 16:15:25 +00:00
northbridge	nb/intel/gm45: Don't run graphics init on s3 resume	2019-10-14 08:16:00 +00:00
security	vboot: create board-specific test-only GBB HWID if not set	2019-09-30 11:33:20 +00:00
soc	soc/intel/skylake/chip: Unhide P2SB device	2019-10-15 08:19:31 +00:00
southbridge	sb/intel/i82801ix: Add common code to set up LPC IO decode ranges	2019-10-14 08:15:49 +00:00
superio	src/superio: Remove unused superio chips	2019-10-13 19:36:23 +00:00
vendorcode	vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support	2019-10-11 07:08:27 +00:00
Kconfig	arch/x86: Add a choice for selecting normal/fallback cbfs prefix	2019-10-08 11:40:25 +00:00