coreboot-kgpe-d16/src
Matt DeVillier 9aaf59aa6d soc/intel/broadwell: decouple PEI memory struct from coreboot header
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.

The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.

Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.

Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31 15:28:12 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch arch/x86/include/arch: Remove space after __attribute__ 2018-05-31 15:28:00 +00:00
commonlib Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00
console Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00
cpu {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate 2018-05-31 15:10:21 +00:00
device device: Move find_dev_path() to device_const.c 2018-05-25 02:45:17 +00:00
drivers i210: Add additional PCI-ID to the i210 driver 2018-05-31 15:27:43 +00:00
ec chromeec platforms: Update ACPI throttle handler call 2018-05-29 22:35:07 +00:00
include cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB 2018-05-31 15:09:30 +00:00
lib Remove AMD K8 cpu and northbridge support 2018-05-31 03:42:11 +00:00
mainboard mainboard/google/kahlee: Add careena variant 2018-05-31 15:25:12 +00:00
northbridge {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate 2018-05-31 15:10:21 +00:00
security security/vboot: Remove redundent _verstage/_everstage/_verstage_size symbols 2018-05-14 16:24:28 +00:00
soc soc/intel/broadwell: decouple PEI memory struct from coreboot header 2018-05-31 15:28:12 +00:00
southbridge Remove VIA vt8237r southbridge support 2018-05-31 03:47:24 +00:00
superio superio/ite/it8720f: Implement power control 2018-05-15 11:47:14 +00:00
vendorcode Remove leftover AMD CIMX RD890 vendorcode 2018-05-24 13:21:32 +00:00
Kconfig cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE 2018-05-31 15:08:48 +00:00