baf27dbaeb
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
21 lines
583 B
Text
21 lines
583 B
Text
# SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_INTEL_I440BX
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bool
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select NO_BOOTBLOCK_CONSOLE
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select NO_CBFS_MCACHE
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config SDRAMPWR_4DIMM
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bool
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depends on NORTHBRIDGE_INTEL_I440BX
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default n
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help
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This option affects how the SDRAMC register is programmed.
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Memory clock signals will not be routed properly if this option
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is set wrong.
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If your board has 4 DIMM slots, you must use select this option, in
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your Kconfig file of the board. On boards with 3 DIMM slots,
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do _not_ select this option.
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