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Change-Id: I9651b24dd68f9a5e324a4532c3cebac32aacca7e Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/c/26885 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Upcoming release - coreboot 4.9
The 4.9 release is planned for November 2018
Update this document with changes that should be in the release notes.
- Please use Markdown.
- See the 4.7 and 4.8 release notes for the general format.
- The chip and board additions and removals will be updated right before the release, so those do not need to be added.
General changes
- Various code cleanups
- Removed
device_tin favor ofstruct device*in ramstage code - Improve adherence to coding style
- Expand use of the postcar stage
- Add bootblock compression capability: on systems that copy the bootblock from very slow flash to ERAM, allow adding a stub that decompresses the bootblock into ERAM to minimize the amount of flash reads
- Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited to POWER8
Added mainboards
- Lenovo W530 Intel Ivybridge
Toolchain
- Update IASL to version 10280531