ad55df9874
Change-Id: I9651b24dd68f9a5e324a4532c3cebac32aacca7e Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/c/26885 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
36 lines
1.1 KiB
Markdown
36 lines
1.1 KiB
Markdown
Upcoming release - coreboot 4.9
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==========================
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The 4.9 release is planned for November 2018
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Update this document with changes that should be in the release
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notes.
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* Please use Markdown.
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* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md)
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release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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General changes
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---------------
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* Various code cleanups
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* Removed `device_t` in favor of `struct device*` in ramstage code
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* Improve adherence to coding style
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* Expand use of the postcar stage
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* Add bootblock compression capability: on systems that copy the bootblock
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from very slow flash to ERAM, allow adding a stub that decompresses the
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bootblock into ERAM to minimize the amount of flash reads
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* Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited
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to POWER8
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Added mainboards
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----------------
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* Lenovo W530 Intel Ivybridge
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Toolchain
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---------
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* Update IASL to version 10280531
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