Matt DeVillier b065e811bd soc/intel/cannonlake: Implement SoC sleep state array ... Adapted from Alderlake implementation, modified as needed. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/hatch (akemi). Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>		2023-10-31 15:06:27 +00:00
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amd	soc/amd/genoa: Add PCI interrupt support	2023-10-31 14:40:22 +00:00
cavium	soc/cavium/cn81xx/bootblock_custom.S: Specify arch	2023-10-20 14:30:54 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel/cannonlake: Implement SoC sleep state array	2023-10-31 15:06:27 +00:00
mediatek	device/device.h: Rename pci_domain_scan_bus	2023-10-20 14:24:57 +00:00
nvidia	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
qualcomm	device/device.h: Rename pci_domain_scan_bus	2023-10-20 14:24:57 +00:00
rockchip	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
samsung	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
sifive/fu540	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00