coreboot-kgpe-d16/src
Edward O'Callaghan b06eaf76b5 vendorcode/amd/agesa: Use F15TN AGESA for F15RL
For the moment we make use of Trinity f15tn AGESA for Richland
f15rl support until we have properly worked out the discrepancies.

Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup.

We later wish to merge f15tn and f15rl support into the AGESA in
any case.

Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7559
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2014-11-27 11:28:05 +01:00
..
arch build system: unify linker use across gcc and clang 2014-11-25 08:47:41 +01:00
console Replace includes of build.h with version.h 2014-11-20 07:28:37 +01:00
cpu cpu/amd/agesa/family15rl: Provide Richland CPU support 2014-11-27 11:27:51 +01:00
device device/dram/ddr3.c: Fix sizeof on array func param overflow 2014-11-08 07:09:34 +01:00
drivers usbdebug: Some fix for dongle compatibility 2014-11-23 20:36:53 +01:00
ec {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs 2014-10-27 23:40:05 +01:00
include Export board-status info. 2014-11-26 23:18:47 +01:00
lib Export board-status info. 2014-11-26 23:18:47 +01:00
mainboard sandy/ivy: Remove explicit setting of HAVE_SMI_HANDLER. 2014-11-26 23:19:23 +01:00
northbridge northbridge/amd/agesa/family15rl: Provide Richland support 2014-11-27 11:27:45 +01:00
soc intel: Remove IRQ1 from possible PIRQ assignemnt. 2014-11-25 23:47:20 +01:00
southbridge ibexpeak: Don't check for CONFIG_HAVE_SMI_HANDLER. 2014-11-26 23:19:29 +01:00
superio superio/ite: Use common dispatch for pnp entry/exit functions 2014-11-04 11:36:32 +01:00
vendorcode vendorcode/amd/agesa: Use F15TN AGESA for F15RL 2014-11-27 11:28:05 +01:00
Kconfig AMD: Move RAMBASE and RAMTOP 2014-11-14 15:46:57 +01:00