coreboot-kgpe-d16/src/arch
Jonathan Neuschäfer cc5be8b72b arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.

The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.

Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02 23:35:49 +02:00
..
arm src/arch: Capitalize CPU, RAM and ROM 2016-07-31 18:35:09 +02:00
arm64 arm64: Add stack dump to exception handler 2016-05-24 20:51:28 +02:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
riscv arch/riscv: Add include/arch/barrier.h 2016-08-02 23:35:49 +02:00
x86 Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00