Patrick Georgi b4a6ca96c0 imgtec/pistachio: Add comment on the unusual memory layout ... To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-05-07 13:53:15 +02:00
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include/soc	imgtec/pistachio: Add comment on the unusual memory layout	2015-05-07 13:53:15 +02:00
bootblock.c	urara: Identity map DRAM/SRAM	2015-04-21 08:12:13 +02:00
cbmem.c	pistachio: set correct CBMEM top address	2015-04-09 02:30:53 +02:00
clocks.c	pistachio: add clock setup for all I2C interfaces	2015-04-21 08:23:37 +02:00
ddr2_init.c	imgtec/pistachio: DDR reads return to controller with no bubbles	2015-04-22 08:59:53 +02:00
Kconfig	soc: select generic gpio lib on (almost) all non-x86 SOCs	2015-04-22 08:54:56 +02:00
Makefile.inc	kbuild: automatically include SOCs	2015-04-29 18:11:30 +02:00
monotonic_timer.c	pistachio: add timer frequency for SOC; correct platform ID	2015-04-09 02:32:59 +02:00
romstage.c	pistachio: add DDR2 initialization code	2015-04-17 10:07:07 +02:00
soc.c	pistachio: add SOC descriptor	2015-04-09 02:32:31 +02:00
spi.c	imgtec/pistachio: Add spi_crop_chunk()	2015-04-21 08:08:05 +02:00
uart.c	pistachio: Move console UART to a Kconfig variable	2015-04-17 10:11:45 +02:00