coreboot-kgpe-d16/src
Subrata Banik b5bea526ec mb/google/hatch: Disable dynamic clock gating for cr50's GPIO
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.

BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.

Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12 02:17:00 +00:00
..
acpi
arch acpigen: Add support for IndexField 2019-06-09 17:20:28 +00:00
commonlib cbmem: Add ID for UCSI 2019-06-07 20:50:39 +00:00
console console: Allow using vprintk() with disabled console 2019-06-11 17:29:02 +00:00
cpu Rampayload: Able to build coreboot without ramstage 2019-06-11 15:49:25 +00:00
device src/device: Prevent attack on null pointer dereference 2019-06-03 13:25:25 +00:00
drivers spi_flash: Add Dual SPI support 2019-06-10 18:02:33 +00:00
ec ec/google/wilco: Add UCSI support 2019-06-07 20:51:16 +00:00
include console: Allow using vprintk() with disabled console 2019-06-11 17:29:02 +00:00
lib lib/Makefile.inc: Add hexdump.c to postcar stage 2019-06-05 13:02:57 +00:00
mainboard mb/google/hatch: Disable dynamic clock gating for cr50's GPIO 2019-06-12 02:17:00 +00:00
northbridge nb/intel/sandybridge: Drop iommu.c and rename functions 2019-06-08 11:32:42 +00:00
security post_code: add post code for failure to load next stage 2019-05-22 14:21:57 +00:00
soc soc/amd/common: Add errors for invalid AcpiMmio access 2019-06-11 14:39:05 +00:00
southbridge sb/amd/sb700: Fix misleading formatting 2019-06-07 21:30:57 +00:00
superio superio/fintek/f71863fg: Remove variable set but not used 2019-05-25 18:20:15 +00:00
vendorcode vendorcode/intel/../icelake: Update ICL FSP header BIOS version 3092 2019-06-09 02:46:52 +00:00
Kconfig Rampayload: Able to build coreboot without ramstage 2019-06-11 15:49:25 +00:00