coreboot-kgpe-d16/src/northbridge
Timothy Pearson 86f4ca5b4b cpu/amd/model_10xxx: Add support for early cbmem
mainboards/amd/fam10: Initialize cbmem area after raminit

When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.

The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage.  TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward.  As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.

TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.

Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 08:28:43 +01:00
..
amd cpu/amd/model_10xxx: Add support for early cbmem 2015-03-19 08:28:43 +01:00
dmp CBMEM: Tag chipsets with LATE_CBMEM_INIT 2015-01-27 22:47:00 +01:00
intel bootstate: use structure pointers for scheduling callbacks 2015-03-18 16:41:43 +01:00
rdc CBMEM: Tag chipsets with LATE_CBMEM_INIT 2015-01-27 22:47:00 +01:00
via x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
Kconfig Add support for DMP Vortex86EX PCI northbridge. 2013-06-22 17:33:27 +02:00
Makefile.inc Add support for DMP Vortex86EX PCI northbridge. 2013-06-22 17:33:27 +02:00