Hannah Williams ba0fc470dd soc/intel/common: Add common smihandler code ... Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-05-25 19:09:00 +02:00
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apollolake	soc/intel/apollolake: add support for writing logical boot partition 2	2016-05-23 17:37:11 +02:00
baytrail	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	2016-05-06 16:50:00 +02:00
braswell	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	2016-05-06 16:50:00 +02:00
broadwell	{cpu,soc}/intel: remove unused smm_init() function	2016-05-06 16:48:21 +02:00
common	soc/intel/common: Add common smihandler code	2016-05-25 19:09:00 +02:00
fsp_baytrail	{cpu,soc}/intel: remove unused smm_init() function	2016-05-06 16:48:21 +02:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: convert to using common MP init	2016-05-06 16:41:01 +02:00
quark	soc/intel/quark: Add USB device port support	2016-05-25 00:17:34 +02:00
sch	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
skylake	skylake: Add handler for finding ACPI path for GPIO	2016-05-21 06:02:11 +02:00