coreboot-kgpe-d16/src/southbridge/intel
Kyösti Mälkki 3d0288d676 intel/i82801dx: Support 2MiB FWH part
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.

Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17918
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-10 13:25:57 +01:00
..
bd82x6x buildsystem: Drop explicit (k)config.h includes 2016-12-08 19:46:53 +01:00
common sb/intel/common/gpio: Support ICH9M and prior 2017-01-03 15:10:15 +01:00
fsp_bd82x6x intel PCI ops: Remove explicit PCI MMCONF access 2016-12-06 20:44:37 +01:00
fsp_i89xx intel PCI ops: Remove explicit PCI MMCONF access 2016-12-06 20:44:37 +01:00
fsp_rangeley spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
i3100 sb/intel/i3100/lpc.c: Use tab for indents 2016-11-28 01:06:33 +01:00
i82371eb southbridge/intel/i82371eb: transition away from device_t 2016-09-10 04:56:04 +02:00
i82801ax southbridge/intel/i82801ax: transition away from device_t 2016-09-10 04:56:19 +02:00
i82801bx tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
i82801dx intel/i82801dx: Support 2MiB FWH part 2017-01-10 13:25:57 +01:00
i82801ex src/southbridge: Code formating 2016-08-31 20:22:46 +02:00
i82801gx sb/ich7: Use common/gpio.h to set up GPIOs 2017-01-06 18:14:00 +01:00
i82801ix intel/i82801ix: Add HAVE_INTEL_FIRMWARE 2016-12-18 20:39:15 +01:00
i82870 src/southbridge: Code formating 2016-08-31 20:22:46 +02:00
ibexpeak intel PCI ops: Remove explicit PCI MMCONF access 2016-12-06 20:43:17 +01:00
lynxpoint PCI ops: Define read-modify-write routines globally 2016-12-06 20:45:22 +01:00