coreboot-kgpe-d16/src/soc
Angel Pons ef879a8f30 soc/skylake: do not rely on P2SB data to generate DRHD
The P2SB PCI device can be "hidden", which causes all sorts of
nightmares and bugs. Moreover, FSP tends to hide it, so finding
a good solution to this problem is impossible with FSP into the mix.

Since the values for IBDF and HBDF were already hardcoded as FSP
parameters, define them as macros and use these values directly to
generate the DRHD.

Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-03 09:51:07 +00:00
..
amd lib/bootblock: Add simplified entry with basetime 2019-08-26 21:11:31 +00:00
cavium arm64: Rename arm_tf.c/h to bl31.c/h 2019-08-30 10:37:17 +00:00
imgtec arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
intel soc/skylake: do not rely on P2SB data to generate DRHD 2019-09-03 09:51:07 +00:00
mediatek mediatek/mt8183: Remove unnecessary parentheses 2019-09-02 06:42:08 +00:00
nvidia arm64: Rename arm_tf.c/h to bl31.c/h 2019-08-30 10:37:17 +00:00
qualcomm ipq40xx: Increase CBFS and RAMSTAGE size 2019-08-30 10:43:42 +00:00
rockchip arm64: Rename arm_tf.c/h to bl31.c/h 2019-08-30 10:37:17 +00:00
samsung arch/non-x86: Use ENV_ROMSTAGE_OR_BEFORE 2019-08-26 21:04:42 +00:00
sifive soc/sifive/fu540: add code for spi and map flash to memory spaces 2019-08-12 08:35:17 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00