Arthur Heymans bf53acca5e nb/intel/x4x: Move boilerplate romstage to a common location ... This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-11-15 16:41:52 +00:00
..
acpi
acpi_tables.c
board_info.txt
cmos.default
cmos.layout
data.vbt
devicetree.cb	sb/intel/i82801jx: Add common code for LPC decode	2019-11-12 18:23:07 +00:00
dsdt.asl
gma-mainboard.ads
gpio.c
hda_verb.c
Kconfig
Kconfig.name
Makefile.inc
romstage.c	nb/intel/x4x: Move boilerplate romstage to a common location	2019-11-15 16:41:52 +00:00