coreboot-kgpe-d16/src/southbridge
Felix Held 70d1c723f7 sb/amd/pi/hudson: remove unused Bolton PI FCH code
There is no nb/amd/pi northbridge left in coreboot that could be paired
with the Bolton FCH, since the remaining nb/amd/pi northbridges all use
an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton
is a discrete FCH. I ran into this when verifying if the common soc/amd
GPIO functionality that gets added by selecting
SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it
and that code isn't valid for Bolton that uses the old GPIO 100
interface.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:06:29 +00:00
..
amd sb/amd/pi/hudson: remove unused Bolton PI FCH code 2021-04-11 21:06:29 +00:00
intel sb/intel/x/smbus.c: Correct register access width 2021-04-11 21:04:46 +00:00
ricoh/rl5c476 src/southbridge: Drop unneeded empty lines 2020-09-21 16:29:35 +00:00
ti sb/ti/pcixx12: Remove NOOP chip driver 2021-03-05 10:58:33 +00:00