1d14b3e926
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
96 lines
1.7 KiB
Text
96 lines
1.7 KiB
Text
/*
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* This file is part of the coreboot project.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* ITSS */
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/* Define the needed ITSS registers used by ASL on Interrupt */
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Scope (\_SB)
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{
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OperationRegion (ITSS, SystemMemory, 0xfdc43100, 0x8)
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Field (ITSS, ByteAcc, NoLock, Preserve)
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{
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PARC, 8,
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PBRC, 8,
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PCRC, 8,
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PDRC, 8,
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PERC, 8,
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PFRC, 8,
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PGRC, 8,
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PHRC, 8,
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}
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/*
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* Pin# = group_pad# + group# * 24.
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* For instance, GPP_A_6 would be pin#6,
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* GPP_D_23 would be 23+(3*24), pin#95.
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*/
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Name (GPPG, Package (0x02)
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{
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Package (0x08)
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{
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0x18,
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0x18,
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0x18,
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0x18,
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0x18,
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0x18,
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0x08,
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0x0C
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},
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Package (0x0A)
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{
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0x18,
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0x18,
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0x18,
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0x18,
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0x0D,
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0x18,
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0x18,
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0x18,
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0x0B,
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0x0C
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}
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})
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Method (GNMB, 1, Serialized)
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{
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Return (And (Arg0, 0xFFFF))
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}
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Method (GGRP, 1, Serialized)
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{
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ShiftRight (And (Arg0, 0x00FF0000), 0x10, Local0)
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Return (Local0)
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}
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/* Convert GPIO PAD name to GPIO number */
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Method (INUM, 1, NotSerialized)
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{
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Store (One, Local0)
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Store (GNMB (Arg0), Local1)
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Store (GGRP (Arg0), Local2)
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Store (Zero, Local3)
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While (LLess (Local3, Local2))
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{
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Add (DerefOf (Index (DerefOf (Index
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(GPPG, Local0)), Local3)),
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Local1, Local1)
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Increment (Local3)
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}
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Return (Add (0x18, Mod (Local1, 0x60)))
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}
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}
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