coreboot-kgpe-d16/src/soc/intel/skylake
Aaron Durbin af030503e8 skylake: fix SMI GPI status handling
The current construction for processing SMI GPI events
didn't allow for the mainboard to query the state of a
particular GPI for the snapshotted SMI event. The
skylake part can route GPIs from any (there are design
limitations) GPIO group. Those status and enable registers
are within the GPIO community so one needs to gather
all the possibilities in order to query the state.

The call chain did this:
southbridge_smi_gpi(
	clear_alt_smi_status() -> reset_alt_smi_status() ->
	print_all_smi_status() -> return 0)

As a replacement the following functions and types are
introduced:

struct gpi_status - represent gpi status.
gpi_status_get() - per gpi query on struct gpi_status
gpi_clear_get_smi_status() - clear and retrieve SMI GPI status
mainboard_smi_gpi_handler() - mainboard handler using gpi_status

Also remove gpio_enable_all_smi() as that construct was never
used, but it also is quite heavy handed in that it would
enable SMI generation for all GPIs.

BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built.

Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291933
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:21:16 +02:00
..
acpi Skylake: Add ASL code to enable GPIO controller 2015-08-14 15:17:53 +02:00
bootblock skylake: fix garbled patch from upstream 2015-08-13 16:11:26 +02:00
include/soc skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
microcode skylake: Rework microcode include path 2015-07-29 18:25:01 +02:00
romstage skylake: pass IED_REGION_SIZE Kconfig to FSP 2015-08-14 15:19:35 +02:00
acpi.c skylake: provide clarification for FADT gpe0_blk_len 2015-08-14 15:20:57 +02:00
chip.c skylake: remove the redundant fspNotify in chip final. 2015-07-29 19:13:36 +02:00
chip.h skylake: remove ec_smi_gpio and alt_gp_smi_en 2015-08-14 15:20:46 +02:00
cpu.c skylake: Update microcode reload in ramstage. 2015-07-29 20:26:35 +02:00
cpu_info.c
elog.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
finalize.c
flash_controller.c
gpio.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
igd.c
Kconfig skylake: provide native gpio functionality 2015-08-14 15:13:15 +02:00
lpc.c
Makefile.inc skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
memmap.c intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
monotonic_timer.c
pch.c
pcie.c
pcr.c skylake: provide pcr helper to get a port's register space 2015-07-29 19:30:49 +02:00
pei_data.c skylake: clean-up pei_data 2015-07-29 19:31:31 +02:00
pmc.c skylake: remove ec_smi_gpio and alt_gp_smi_en 2015-08-14 15:20:46 +02:00
pmutil.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
ramstage.c
smbus.c
smbus_common.c
smi.c
smihandler.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
smmrelocate.c skylake: use smm_subregion() during SMM relocation 2015-08-14 15:19:24 +02:00
systemagent.c intel fsp: remove CHIPSET_RESERVED_MEM_BYTES 2015-07-21 20:09:31 +02:00
tsc_freq.c
uart.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
uart_debug.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
xhci.c