Felix Held c0dbd4cb56 soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers ... Picasso has 32 configurable GPEs, not only 28. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-02-04 00:10:20 +00:00
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amd	soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers	2021-02-04 00:10:20 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/tgl: Add configurable value for ConfigTdpLevel	2021-02-03 20:11:06 +00:00
mediatek	src: Remove unused <boardid.h>	2021-02-03 08:56:39 +00:00
nvidia	soc/nvidia/tegra124/spi.c: Remove repeated word	2021-01-18 07:35:02 +00:00
qualcomm	src: Remove unused <boardid.h>	2021-02-03 08:56:39 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	soc/samsung/exynos{5250,5420}/include/soc/cpu.h: Add missing include	2021-02-01 08:59:29 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	soc/ti/am335x/header.c: Add missing include	2021-02-03 08:55:15 +00:00
ucb