Ronak Kanabar c4813ea260 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 ... The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-16 22:17:26 +00:00
..
acpi	soc/intel/alderlake: Skip D3Cold for TBT	2021-04-10 12:00:33 +00:00
bootblock	soc/intel/alderlake: Update CPU and IGD Device IDs	2021-05-14 09:03:01 +00:00
include/soc	soc/intel/alderlake: Add known CPU Port IDs for GPIO communities	2021-05-14 08:57:57 +00:00
romstage	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
spd	util: Add new memory part to LP4x list	2021-03-03 15:50:47 +00:00
acpi.c	soc/intel/alderlake: Use device ID from pci_devs header file	2021-04-26 08:27:54 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/alderlake: remove duplicate PL2 override	2021-05-04 15:03:44 +00:00
chipset.cb	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog.c	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c
fsp_params.c	soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC	2021-04-16 06:44:28 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
lockdown.c
Makefile.inc	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
me.c
meminit.c	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00	2021-05-16 22:17:26 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c
spi.c
systemagent.c	soc/intel/alderlake: add processor power limits control support	2021-03-28 16:08:02 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	2021-02-24 11:27:51 +00:00