coreboot-kgpe-d16/src
Wolfgang Kamp 9ae1eb6961 Super I/O W83627DHG: Enable UART B by redirecting pins
Pins 78-85 are set to GPIO after power on or reset. To enable
UART B the pins must be redirected to it.

Look at W83627DHG databook version 1.4 page 185 Chip
(global) Control Register CR2C.

Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
Reviewed-on: http://review.coreboot.org/2626
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-15 17:51:48 +01:00
..
arch x86: improve lb_cleanup_memory_ranges 2013-03-14 20:13:19 +01:00
console Eliminate do_div(). 2013-03-08 23:14:26 +01:00
cpu haswell: Add ULT CPUID and updated microcode 2013-03-14 18:24:27 +01:00
device GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
drivers GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
ec Support ITE IT8518 embedded controller running Quanta's firmware 2013-03-14 04:54:21 +01:00
include haswell: reserve default SMRAM space 2013-03-15 16:58:37 +01:00
lib Eliminate do_div(). 2013-03-08 23:14:26 +01:00
mainboard Persimmon DSDT: Remove INI method from AZHD device 2013-03-15 17:07:01 +01:00
northbridge haswell: Fix BDSM and BGSM indicies in memory map 2013-03-15 16:58:54 +01:00
southbridge lynxpoint: lpc resource reservations 2013-03-14 20:18:57 +01:00
superio Super I/O W83627DHG: Enable UART B by redirecting pins 2013-03-15 17:51:48 +01:00
vendorcode AGESA: Fix CR0_PE bit define 2013-03-08 07:30:06 +01:00
Kconfig bump SeaBIOS to 1.7.2.1 2013-03-04 11:00:17 +01:00