Angel Pons c4ee714881 nb/intel/haswell: Use unshifted SPD addresses in mainboards ... It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-03-23 10:59:26 +00:00
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acpi
acpi_tables.c	ACPI: Select ACPI_SOC_NVS only where suitable	2021-01-18 07:21:34 +00:00
board_info.txt
data.vbt
devicetree.cb	cpu/intel/haswell: Factor out ACPI C-state values	2021-01-15 11:23:23 +00:00
dsdt.asl	ACPI: Add top-level ASL	2021-01-27 15:35:13 +00:00
gma-mainboard.ads
gpio.c	lynxpoint/broadwell: Rename LP GPIO config global	2021-03-22 11:26:22 +00:00
hda_verb.c
Kconfig
Kconfig.name
Makefile.inc
romstage.c	nb/intel/haswell: Use unshifted SPD addresses in mainboards	2021-03-23 10:59:26 +00:00