Subrata Banik c66733a106 soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboard ... This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-08-19 17:30:16 +00:00
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spd	mb/intel/shadowmountain: Add the romstage code	2021-02-22 05:46:58 +00:00
variants/baseboard	mb/intel/sm: Skip FSP to program UART0	2021-06-23 09:08:50 +00:00
board_info.txt
bootblock.c	mb/intel/shadowmountain: Add bootblock and verstage code	2021-02-06 09:09:16 +00:00
chromeos.c	mb/intel/shadowmountain: Add bootblock and verstage code	2021-02-06 09:09:16 +00:00
chromeos.fmd	mb/intel/shadowmountain: Add flash layout	2021-01-28 03:11:35 +00:00
dsdt.asl	mb/intel/shadowmountain: Add the ASL code	2021-02-27 09:40:57 +00:00
ec.c	mb/intel/shadowmountain: Add the ramstage code	2021-02-27 09:40:47 +00:00
Kconfig	soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboard	2021-08-19 17:30:16 +00:00
Kconfig.name
mainboard.c	mb/intel/shadowmountain: Add the ramstage code	2021-02-27 09:40:47 +00:00
Makefile.inc	mb/intel/shadowmountain: Add the ramstage code	2021-02-27 09:40:47 +00:00
romstage.c	soc/intel/alderlake: Update mainboard_memory_init_params() argument	2021-06-24 07:55:12 +00:00
smihandler.c	mb/intel/shadowmountain: Add the ramstage code	2021-02-27 09:40:47 +00:00