coreboot-kgpe-d16/src/soc
Brandon Breitenstein c6ec8dd1cb fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms

Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21 23:43:28 +01:00
..
broadcom/cygnus soc/broadcom/cygnus: Update DDR Kconfig 2016-11-17 17:57:09 +01:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel fsp2_0: implement stage cache for silicon init 2016-11-21 23:43:28 +01:00
lowrisc/lowrisc riscv: add the lowrisc System On Chip support 2016-10-25 22:31:06 +02:00
marvell marvell/mvmap2315: Compose BOOTBLOCK region 2016-10-21 19:42:23 +02:00
mediatek/mt8173 src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
nvidia soc/nvidia/tegra210: Remove CONSOLE_SERIAL_TEGRA210_UART_CHOICES 2016-11-14 18:10:57 +01:00
qualcomm soc/qualcomm/ipq40xx: Fix GPIO pull up config. 2016-10-07 17:55:19 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: Change 933 DPLL to low jitter rate 2016-11-17 17:59:22 +01:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:24:42 +02:00