coreboot-kgpe-d16/src/arch/riscv
Jonathan Neuschäfer cc5be8b72b arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.

The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.

Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02 23:35:49 +02:00
..
include arch/riscv: Add include/arch/barrier.h 2016-08-02 23:35:49 +02:00
boot.c arch/riscv: Unconditionally start payloads in machine mode 2016-07-14 18:23:27 +02:00
bootblock.S arch/riscv: Refactor bootblock.S 2016-07-28 18:31:28 +02:00
bootblock_simple.c arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
id.ld arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
id.S arch/riscv: Refactor bootblock.S 2016-07-28 18:31:28 +02:00
Kconfig console: Simplify bootblock console Kconfig selection logic 2016-01-21 05:37:27 +01:00
Makefile.inc arch/riscv: Refactor bootblock.S 2016-07-28 18:31:28 +02:00
misc.c arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
prologue.inc tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
stages.c arch: remove stage_exit() 2016-02-11 23:12:06 +01:00
tables.c lib: add common write_tables() implementation 2016-04-21 20:49:05 +02:00
trap_handler.c arch/riscv: Enable unaligned load handling 2016-07-19 20:22:25 +02:00
trap_util.S arch/riscv: Change all eret instructions to .word 0x30200073 (mret) 2016-07-18 22:50:33 +02:00
virtual_memory.c arch/riscv: Add include/arch/barrier.h 2016-08-02 23:35:49 +02:00