c0fd6e5ea6
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register, the NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space always reads back as 0x7f. [1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev 3.01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
29 lines
666 B
C
29 lines
666 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <cf9_reset.h>
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#include <reset.h>
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#include <soc/southbridge.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/reset.h>
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void do_cold_reset(void)
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{
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/* De-assert and then assert all PwrGood signals on CF9 reset. */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CPU | SYS_RST, RST_CNT);
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}
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void do_warm_reset(void)
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{
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/* Warm resets are not supported and must be executed as cold */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CPU | SYS_RST, RST_CNT);
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}
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void do_board_reset(void)
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{
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do_cold_reset();
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}
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