coreboot-kgpe-d16/src/soc/amd/cezanne
Raul E Rangel 54786fece8 soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.

replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.

I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.

BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:23:35 +00:00
..
acpi soc/amd/common/block/i2c: Add support for shared TPM_I2C controller 2022-02-17 23:14:02 +00:00
include/soc soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER 2022-03-09 19:01:15 +00:00
psp_verstage soc/amd/cezanne/psp_verstage: Log the platform boot mode report 2022-03-10 15:16:32 +00:00
acpi.c soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_core 2022-01-26 04:15:11 +00:00
agesa_acpi.c soc/amd/cezanne: Generate IVRS for cezanne 2021-08-05 15:54:50 +00:00
aoac.c soc/amd/cezanne: factor out AOAC offset defines 2021-06-16 16:38:25 +00:00
bootblock.c soc/amd/cezanne,picasso: factor out common early non-car cache setup 2022-01-20 22:28:50 +00:00
chip.c soc/amd/cezanne/chip: add functionality to power down eMMC interface 2021-08-29 20:58:51 +00:00
chip.h soc/amd/*/i2c: factor out common I2C pad configuration 2022-02-03 23:46:00 +00:00
chipset.cb soc/amd/cezanne,picasso/chipset.cb: drop LAPIC device 2021-10-22 14:59:24 +00:00
config.c src: Add missing 'void' in function definition 2022-01-26 23:57:12 +00:00
cppc.c acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table 2021-10-21 20:03:14 +00:00
cpu.c cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
data_fabric.c src: Make PCI ID define names shorter 2022-03-07 08:32:09 +00:00
early_fch.c src/soc/amd: Remove unused <console/console.h> 2022-01-10 18:40:56 +00:00
espi_util.c soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions 2022-01-14 00:29:52 +00:00
fch.c soc/amd/cezanne/fch: disable 48MHz output in S0i3 2021-12-20 17:39:29 +00:00
fsp_m_params.c soc/amd/cezanne: FSP: Add UPD entry for eDP tuning 2022-01-25 23:57:06 +00:00
fsp_s_params.c soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE 2021-07-19 14:58:53 +00:00
fw.cfg soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD 2022-02-21 21:29:50 +00:00
gpio.c soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h 2021-09-23 18:33:00 +00:00
graphics.c soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo 2021-07-17 21:32:59 +00:00
i2c.c treewide: Remove "ERROR: "/"WARN: " prefixes from log messages 2022-02-07 23:29:09 +00:00
Kconfig drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs 2022-02-18 20:21:45 +00:00
Makefile.inc soc/amd/cezanne: Allow to specify SPL table path in Kconfig 2022-02-12 17:07:09 +00:00
mca.c soc/amd/cezanne/mca: add and use mca_bank_name[] 2021-07-21 22:38:11 +00:00
preload.c soc/amd/cezanne: Preload FSP-S 2021-11-12 14:55:45 +00:00
reset.c soc/amd/cezanne: remove warm reset flag code 2021-06-11 21:48:28 +00:00
romstage.c timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
root_complex.c src: Make PCI ID define names shorter 2022-03-07 08:32:09 +00:00
smihandler.c soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem 2022-03-10 17:23:35 +00:00
smu.c soc/amd/cezanne: add SMU support 2021-03-04 19:55:27 +00:00
uart.c soc/amd/cezanne,picasso/uart: implement read_resource 2021-10-15 14:46:58 +00:00
xhci.c soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h 2021-09-23 18:33:00 +00:00