V Sowmya 752dc8e425 soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros ... Rename BAR0 and BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_0 -> SRAM_BASE_0 * PMC_SRAM_SIZE_0 -> SRAM_SIZE_0 * PMC_SRAM_BASE_1 -> SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> SRAM_SIZE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20539 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2017-08-15 23:11:16 +00:00
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cpu.asl
dptf.asl
globalnvs.asl	soc/intel/apollolake: Enable UART debug controller on S3 resume	2017-08-10 16:25:14 +00:00
gpio.asl	soc/intel/apollolake: Use common gpio for apollolake	2017-07-03 23:29:49 +00:00
gpiolib.asl	soc/intel/apollolake: Bring in delta for GLK SOC	2017-07-21 03:59:09 +00:00
lpc.asl
lpss.asl
northbridge.asl
pch_hda.asl
pci_irqs.asl	soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK	2017-07-28 16:27:53 +00:00
pcie.asl
platform.asl	soc/intel/apollolake: Implement _PIC method into ACPI	2017-07-20 04:44:41 +00:00
pmc_ipc.asl	soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros	2017-08-15 23:11:16 +00:00
scs.asl	soc/intel/apollolake: Set sdcard card detect (CD) host ownership	2017-04-13 19:50:34 +02:00
sleepstates.asl
soc_int.asl	soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK	2017-07-28 16:27:53 +00:00
southbridge.asl	soc/intel/apollolake: Use common PCR module	2017-04-10 20:05:35 +02:00
xhci.asl