Sridhar Siricilla d16187ed2a soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command ... Below changes are done: 1. Allow execution of HMRFPO_ENABLE command if CSE meets below prerequisites: - Current operation mode(COM) is Normal and Curret working state(CWS) is Normal. -(or) COM is Soft Temp Disable and CWS is Normal if ME's Firmware SKU is Custom. 2. Check response status. 3. Add documentation for send_hmrfpo_enable_msg(). 4. Rename padding field of hmrfpo_enable_resp to reserved. The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perform updates to it. This command is only valid before EOP(End of Post). For Custom SKU, follow below procedure to place CSE in HMRFPO mode: 1. Ensure CSE boots from BP1. When CSE boots from BP1, it will have opmode Temp Disable Mode. 2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode. CSE Firmware Custom SKU Image Layout: = [RO] + [RW + DATA PART] = [BP1] + [BP2 + DATA PART] Here, BP1 will have reduced functionality of BP2, and the BP1 will be CSE's RO partition and [BP2 + DATA PART] together will represent CSE's RW partition. CSE can boot from either BP1(RO) or BP2(RW). CSE Image Layout in Consumer SKU: BP2 + BP3 + DATA PART TEST=Verfied on hatch board. Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-03-15 13:10:36 +00:00
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apollolake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
baytrail	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
braswell	soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries	2020-03-09 11:03:41 +00:00
broadwell	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
cannonlake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
common	soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command	2020-03-15 13:10:36 +00:00
denverton_ns	soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling	2020-03-10 20:45:53 +00:00
icelake	soc/intel/icelake: Re-flow comment for 96 characters	2020-03-15 12:57:02 +00:00
quark	soc/intel: Add get_pmbase	2020-02-04 18:54:01 +00:00
skylake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
tigerlake	soc/intel/tigerlake: Match RP number with TGL EDS	2020-03-15 12:56:21 +00:00
xeon_sp	soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries	2020-03-10 11:52:45 +00:00
Kconfig	soc/intel: Add Intel Xeon Scalable Processor support	2020-03-06 08:19:59 +00:00