coreboot-kgpe-d16/src/soc
Julius Werner d3600b1405 rockchip/rk3399: Move TTB to the end of SRAM
We found that we may want to load some components of BL31 on the RK3399
into SRAM. As usual, these components may not overlap any coreboot
regions still in use at that time, as is already statically checked by
the check-ramstage-overlaps rule in Makefile.inc.

On RK3399, the only such regions are TTB and STACK. This patch moves the
TTB region back to the end of SRAM (right before STACK), so that a large
contiguous region of SRAM before that remains usable for BL31.

BRANCH=gru
BUG=None
TEST=Booted Kevin.

Change-Id: I1689d0280d79bad805fea5fc3759c2ae3ba24915
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1d4c6c6f6cc0efe97d6962a81e309a1c040d1def
Original-Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/384635
Original-Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-on: https://review.coreboot.org/16714
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06 21:51:08 +02:00
..
broadcom/cygnus soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. 2016-08-31 20:23:34 +02:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00
marvell soc/marvell/mvmap2315: Add DDR driver 2016-09-13 17:03:53 +02:00
mediatek/mt8173 src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
nvidia Makefiles: update cbfs types from bare numbers to values 2016-09-21 09:36:11 +02:00
qualcomm src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
rdc/r8610
rockchip rockchip/rk3399: Move TTB to the end of SRAM 2016-10-06 21:51:08 +02:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:24:42 +02:00