coreboot-kgpe-d16/src/mainboard/google/veyron_pinky
David Hendricks b4ff291cf6 rk3288: Pass SPI bus speed in as parameter to init function
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.

BUG=none
BRANCH=none
TEST=built and booted on Pinky

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Original-Reviewed-on: https://chromium-review.googlesource.com/220411
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

(cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c
Reviewed-on: http://review.coreboot.org/9245
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04 04:03:18 +02:00
..
sdram_inf coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz 2015-04-02 21:16:55 +02:00
board.h veyron_pinky: Add rev2 support, clean up mainboard.c 2015-04-02 20:46:26 +02:00
boardid.c veyron_pinky: Add board ID support 2015-03-24 15:27:13 +01:00
bootblock.c rk3288: Pass SPI bus speed in as parameter to init function 2015-04-04 04:03:18 +02:00
chromeos.c veyron_pinky: Add rev2 support, clean up mainboard.c 2015-04-02 20:46:26 +02:00
devicetree.cb
Kconfig rk3288/pinky: Move uart address to mainboard Kconfig 2015-04-02 23:27:09 +02:00
mainboard.c rockchip: support i2c clock setting 2015-04-02 21:16:28 +02:00
Makefile.inc veyron_pinky: Add rev2 support, clean up mainboard.c 2015-04-02 20:46:26 +02:00
reset.c veyron_pinky: Add rev2 support, clean up mainboard.c 2015-04-02 20:46:26 +02:00
romstage.c rockchip: support pwm regulator 2015-04-02 21:16:45 +02:00
sdram_configs.c coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz 2015-04-02 21:16:55 +02:00