coreboot-kgpe-d16/src/soc/rockchip
Lin Huang 4ecccff72f rockchip/rk3399: set edp pclk to 25MHz
It may cause an edp aux transfer error if the edp pclk is
set too high, so reduce it to 25MHz.

BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot

Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596
Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/429410
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24 09:34:04 +01:00
..
common rockchip/rk3288: rtc-rk808: fix rtc time reading issue 2017-01-13 17:40:56 +01:00
rk3288 soc/rockchip: split edp_enable() function 2016-11-14 18:08:11 +01:00
rk3399 rockchip/rk3399: set edp pclk to 25MHz 2017-01-24 09:34:04 +01:00