Wim Vervoorn d6b682cf92 soc/intel/skylake: Allow setting of PcieRpMaxPayload ... Add setting of the MaxPayload for each root port from the device tree. By default MaxPayload is set to 128 bytes. This change allows changing to 256 bytes. BUG=N/A TEST=tested on facebook monolith Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>		2020-05-11 09:30:04 +00:00
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apollolake	soc/intel: Replace GPLv2 long form headers with SPDX header	2020-05-08 15:20:28 +00:00
baytrail	vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()	2020-05-09 00:21:59 +00:00
braswell	acpi: Move ACPI table support out of arch/x86 (3/5)	2020-05-02 18:45:16 +00:00
broadwell	vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()	2020-05-09 00:21:59 +00:00
cannonlake	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
common	treewide: replace GPLv2 long form headers with SPDX header	2020-05-06 22:20:57 +00:00
denverton_ns	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
icelake	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
jasperlake	soc/intel/jasperlake: Add ACPI device name for Storage controllers	2020-05-11 08:27:29 +00:00
quark	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
skylake	soc/intel/skylake: Allow setting of PcieRpMaxPayload	2020-05-11 09:30:04 +00:00
tigerlake	soc/intel/tigerlake: Update C-State info	2020-05-11 08:38:07 +00:00
xeon_sp	soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX	2020-05-11 08:29:28 +00:00
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00