Subrata Banik 447233ce8c soc/intel/alderlake: Update UART0 GPIO as per latest schematics ... UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-11-23 03:37:33 +00:00
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acpi	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
bootblock	soc/intel/alderlake: Add PCH ID 0x5181	2020-11-12 03:51:49 +00:00
include/soc	mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'	2020-10-29 10:49:03 +00:00
romstage	soc/intel/alderlake/romstage: Skip GPIO configuration from FSP	2020-10-25 06:18:03 +00:00
acpi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
chip.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
chip.h	mb/*,soc/intel: drop the obsolete dt option speed_shift_enable	2020-10-26 06:51:42 +00:00
cpu.c	soc/intel: deduplicate ACPI timer emulation	2020-10-28 21:28:19 +00:00
elog.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
espi.c	soc/intel/alderlake/ramstage: Fix compilation issue	2020-10-06 12:30:15 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
gpio.c	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	2020-09-27 03:03:25 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Kconfig	soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE	2020-11-23 03:37:04 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'	2020-10-29 10:49:03 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pmc.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
pmutil.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
smmrelocate.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
soundwire.c	mb/intel: Enable ALC711 Audio codec over SNDW0 link	2020-11-07 08:55:53 +00:00
spi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
systemagent.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
uart.c	soc/intel/alderlake: Update UART0 GPIO as per latest schematics	2020-11-23 03:37:33 +00:00